1. Field
The following description relates to a technique for compressing a plurality of instructions.
2. Description of the Related Art
A processor typically includes a plurality of functional units (FUs) that are used to process a plurality of instructions in parallel or simultaneously. The processor may reduce a processing time for instructions by parallel-processing the instructions using the FUs.
The number of instructions that can be parallel-processed in a processor depends on the number of FUs. For example, if there are four FUs, a maximum of four instructions can be processed simultaneously.
For example, a valid instruction is an instruction for executing a predetermined operation. Meanwhile, a no operation (NOP) instruction is for executing no operation and may exist between valid instructions. A compiler included in a processor has to encode NOP operations as well as valid instructions in order to allocate all instructions to the FUs. However, encoding unnecessary NOP operations that have little or no influence on an operation increases the processing load. The increase in the number of instructions that should be encoded also increases the code size, which requires complicated hardware and increases the overhead upon processing of instructions.
Accordingly, there is a need for a technique that efficiently compresses instructions in order for a processor to more efficiently process the instructions.